DIGITAL CLOCK AND CALENDAR on DE2 KIT (verilog code)

Below is the code for a digital clock and calendar written in verilog, which displays on 8 7-segment leds on DE2 KIT.

NOTE : We use SW1 to interchange the display between clock and calendar. And anything so far that u can't understand well, contact me : louiskhanh@gmail.com

module projectclock(
    input clk,              //CLOCK_50
    input reset, //SW0
    input clock_calendar,   //SW1
//for clock
input set_time,         //SW2
    input set_hour,         //SW4
    input set_min,          //SW3
//for calendar
input set_day,          //SW17
input set_month,        //SW16
input set_year0,        //SW12
input set_year1,        //SW13
input set_year2,        //SW14
input set_year3, //SW15
//output
output reg led0,led2,
    output reg [6:0] hex0,hex1,hex2,hex3,hex4,hex5,hex6,hex7

    );

//for clock
reg [5:0] hour;
reg [5:0] min;
reg [5:0] sec;
reg [3:0] hr0,hr1,min0,min1,sec0,sec1;
//for calendar
reg [4:0] day;
reg [3:0] month;
reg [3:0] year1,year2,year3,year0;
reg [3:0] d1,d0,m1,m0;
reg [12:0] year;

wire clk_1hz;
delay(clk,clk_1hz);//generate 1hz clock

always@(posedge clk_1hz,posedge reset)
begin
if(reset==1)
    begin
        hour<=0;min<=0;sec<=0;day<=1;month<=1;year0<=2;year1<=1;year2<=0;year3<=2;
end
else
    begin
if(set_time==0)
begin
led0<=1;//when we don't set time, led0 will blink
            sec<=sec+1;
         
            if(sec==59)
            begin
                sec<=0;
                min<=min+1;
            end
         
            if(min==59&&sec==59)
            begin
sec<=0;
                min<=0;
                hour<=hour+1;
            end
         
if(hour==23&&min==59&&sec==59)
            begin
sec<=0;
min<=0;
hour<=0;
day<=day+1;
end

year=year3*1000+year2*100+year1*10+year0;

if(day==28&&month==2&&hour==23&&min==59&&sec==59&&(year%4)!=0)//in case of month 2 of a normal year
begin month<=3;day<=1;end
else if(day==29&&month==2&&hour==23&&min==59&&sec==59&&(year%4)==0)//in case it's a leaf year
begin month<=3;day<=1;end
else if(day==30&&hour==23&&min==59&&sec==59)//in case of month 4,6,9,11 : we have 30 days
   begin
if(month==4||month==6||month==9||month==11)
begin month<=month+1;day<=1;end
end
else if(day==31&&hour==23&&min==59&&sec==59)//in case of month 1,3,5,7,8,10,12 : we have 30 days
   begin
if(month==1||month==3||month==5||month==7||month==8||month==10||month==12)
begin month<=month+1;day<=1;end
end
end
  else if(set_time==1)
begin
led0<=0;//when we set time, led0 will be off

if(set_hour==1)
begin
if(hour==5'd23)
hour<=0;
else
hour<=hour+1;
end

            if(set_min==1)
            begin
                if(min==6'd59)
                min<=0;
                else
                min<=min+1;
end

if(set_day==1)
begin
if(day==5'd31) //set day
day<=1;
else
day<=day+1;
end

if(set_month==1)
begin
if(month==4'd12)//set month
month<=1;
else
month<=month+1;
end

if(set_year0==1)
begin
if(year0==4'd9) //set year hang don vi
year0<=0;
else
year0<=year0+1;
end

if(set_year1==1)
begin
if(year1==4'd9) //set year hang chuc
year1<=0;
else
year1<=year1+1;
end

if(set_year2==1)
begin
if(year2==4'd9) //set year hang tram
year2<=0;
else
year2<=year2+1;
end

if(set_year3==1)
begin
if(year3==4'd9) //set year hang ngan
year3<=0;
else
year3<=year3+1;
end
end
end
end

always@(posedge clk_1hz)
begin
if(clock_calendar==1)//display clock
begin
led2<=1;//when we choose to display clock,led2 will blink
hex6<=0;
hex7<=0;
bcd (hour,hr1,hr0);//display hour
display (hr0,hex4);
display (hr1,hex5);
bcd (min,min1,min0);//display min
display (min0,hex2);
display (min1,hex3);
bcd (sec,sec1,sec0);//display sec
display (sec0,hex0);
display (sec1,hex1);
    end
    else if(clock_calendar==0)//display calendar
begin
led2<=0;//when we choose to display calendar,led2 will be off
bcd (day,d1,d0);//display day
display (d0,hex6);
display (d1,hex7);
bcd (month,m1,m0);//display month
display (m0,hex4);
display (m1,hex5);
display (year0,hex0);//display year
display (year1,hex1);
display (year2,hex2);
display (year3,hex3);
end
end

task bcd;
input [5:0] bin;
output [3:0] bcd1;
output [3:0] bcd0;

  case (bin)
     6'd0 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0000; end
     6'd1 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0001; end
     6'd2 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0010; end
     6'd3 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0011; end
     6'd4 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0100; end
     6'd5 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0101; end
     6'd6 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0110; end
     6'd7 : begin bcd1 <= 4'b0000; bcd0 <= 4'b0111; end
     6'd8 : begin bcd1 <= 4'b0000; bcd0 <= 4'b1000; end
     6'd9 : begin bcd1 <= 4'b0000; bcd0 <= 4'b1001; end
    6'd10 : begin bcd1 <= 4'b0001; bcd0 <= 4'b0000; end
    6'd11 : begin bcd1 <= 4'b0001; bcd0 <= 4'b0001; end
    6'd12 : begin bcd1 <= 4'b0001; bcd0 <= 4'b0010; end
    6'd13 : begin bcd1 <= 4'b0001; bcd0 <= 4'b0011; end
    6'd14 : begin bcd1 <= 4'b0001; bcd0 <= 4'b0100; end
    6'd15 : begin bcd1 <= 4'b0001; bcd0 <= 4'b0101; end
    6'd16 : begin bcd1 <= 4'b0001; bcd0 <= 4'b0110; end
    6'd17 : begin bcd1 <= 4'b0001; bcd0 <= 4'b0111; end
    6'd18 : begin bcd1 <= 4'b0001; bcd0 <= 4'b1000; end
    6'd19 : begin bcd1 <= 4'b0001; bcd0 <= 4'b1001; end
    6'd20 : begin bcd1 <= 4'b0010; bcd0 <= 4'b0000; end
    6'd21 : begin bcd1 <= 4'b0010; bcd0 <= 4'b0001; end
    6'd22 : begin bcd1 <= 4'b0010; bcd0 <= 4'b0010; end
    6'd23 : begin bcd1 <= 4'b0010; bcd0 <= 4'b0011; end
    6'd24 : begin bcd1 <= 4'b0010; bcd0 <= 4'b0100; end
    6'd25 : begin bcd1 <= 4'b0010; bcd0 <= 4'b0101; end
    6'd26 : begin bcd1 <= 4'b0010; bcd0 <= 4'b0110; end
    6'd27 : begin bcd1 <= 4'b0010; bcd0 <= 4'b0111; end
    6'd28 : begin bcd1 <= 4'b0010; bcd0 <= 4'b1000; end
    6'd29 : begin bcd1 <= 4'b0010; bcd0 <= 4'b1001; end
    6'd30 : begin bcd1 <= 4'b0011; bcd0 <= 4'b0000; end
    6'd31 : begin bcd1 <= 4'b0011; bcd0 <= 4'b0001; end
    6'd32 : begin bcd1 <= 4'b0011; bcd0 <= 4'b0010; end
    6'd33 : begin bcd1 <= 4'b0011; bcd0 <= 4'b0011; end
    6'd34 : begin bcd1 <= 4'b0011; bcd0 <= 4'b0100; end
    6'd35 : begin bcd1 <= 4'b0011; bcd0 <= 4'b0101; end
    6'd36 : begin bcd1 <= 4'b0011; bcd0 <= 4'b0110; end
    6'd37 : begin bcd1 <= 4'b0011; bcd0 <= 4'b0111; end
    6'd38 : begin bcd1 <= 4'b0011; bcd0 <= 4'b1000; end
    6'd39 : begin bcd1 <= 4'b0011; bcd0 <= 4'b1001; end
    6'd40 : begin bcd1 <= 4'b0100; bcd0 <= 4'b0000; end
    6'd41 : begin bcd1 <= 4'b0100; bcd0 <= 4'b0001; end
    6'd42 : begin bcd1 <= 4'b0100; bcd0 <= 4'b0010; end
    6'd43 : begin bcd1 <= 4'b0100; bcd0 <= 4'b0011; end
    6'd44 : begin bcd1 <= 4'b0100; bcd0 <= 4'b0100; end
    6'd45 : begin bcd1 <= 4'b0100; bcd0 <= 4'b0101; end
    6'd46 : begin bcd1 <= 4'b0100; bcd0 <= 4'b0110; end
    6'd47 : begin bcd1 <= 4'b0100; bcd0 <= 4'b0111; end
    6'd48 : begin bcd1 <= 4'b0100; bcd0 <= 4'b1000; end
    6'd49 : begin bcd1 <= 4'b0100; bcd0 <= 4'b1001; end
    6'd50 : begin bcd1 <= 4'b0101; bcd0 <= 4'b0000; end
    6'd51 : begin bcd1 <= 4'b0101; bcd0 <= 4'b0001; end
    6'd52 : begin bcd1 <= 4'b0101; bcd0 <= 4'b0010; end
    6'd53 : begin bcd1 <= 4'b0101; bcd0 <= 4'b0011; end
    6'd54 : begin bcd1 <= 4'b0101; bcd0 <= 4'b0100; end
    6'd55 : begin bcd1 <= 4'b0101; bcd0 <= 4'b0101; end
    6'd56 : begin bcd1 <= 4'b0101; bcd0 <= 4'b0110; end
    6'd57 : begin bcd1 <= 4'b0101; bcd0 <= 4'b0111; end
    6'd58 : begin bcd1 <= 4'b0101; bcd0 <= 4'b1000; end
    6'd59 : begin bcd1 <= 4'b0101; bcd0 <= 4'b1001; end
    6'd60 : begin bcd1 <= 4'b0110; bcd0 <= 4'b0000; end
 
    endcase

  endtask
  task display;
  input [3:0] bcd;
  output [6:0] seg7;

      case(bcd)
        5'h00: seg7 <= 7'b1000000;
        5'h01: seg7 <= 7'b1111001;  
        5'h02: seg7 <= 7'b0100100;  
        5'h03: seg7 <= 7'b0110000;  
        5'h04: seg7 <= 7'b0011001;
        5'h05: seg7 <= 7'b0010010;
        5'h06: seg7 <= 7'b0000010;  
        5'h07: seg7 <= 7'b1111000;  
        5'h08: seg7 <= 7'b0000000;
        5'h09: seg7 <= 7'b0010000;  
       
      endcase
   endtask
endmodule

module delay(clk,clk_1hz);
input clk;
output clk_1hz;
reg clk_1hz;
integer X;

always@(posedge clk)
begin
 if (X==50000000)
  begin
clk_1hz<=1;
X<=0;
end
else
begin
X<=X+1;
clk_1hz<=0;
end
end
endmodule
// written by LouisKhanh